The Description of AT89S51
1 General Description
The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmelrsquo;s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.
The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.
2 Ports
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.
Port 1 also receives the low-order address bytes during Flash programming and verification.
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Port Pin |
Alternate Functions |
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P1.5 |
MOSI (used for In-System Programming) |
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P1.6 |
MOSO (used for In-System Programming) |
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P1.7 |
SCK(used for In-System Programming) |
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the following table.
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Port Pin |
Alternate Functions |
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P3.0 |
RXD(serial input port) |
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P3.1 |
TXD(serial output port) |
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P3.2 |
INT0(external interrupt 0) |
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P3.3 |
INT1(external interrupt 1) |
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P3.4 |
T0(timer 0 external input) |
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P3.5 |
T1(timer 1 external input) |
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P3.6 |
WR(external data memory write strobe) |
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P3.7 |
RD(external data memory read strobe) |
3 Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 3-1.
Table 3-1. AT89S51 SFR Map and Reset Values
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0F8H |
0FFH |
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0F0H |
B 00000000 |
0F7H |
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0E8H |
0EFH |
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0E0H |
ACC 00000000 |
0E7H |
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0D8H |
0DFH |
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0D0H |
PSW 00000000 |
0D7H |
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0C8H 剩余内容已隐藏，支付完成后下载完整资料 AT89S51概述 1 一般概述 AT89S51是一个低功耗，高性能CMOS8位微控制器,可在4K字节的系统内编程的闪存存储器。该设备是采用Atmel的高密度非易失性存储器技术，与工业标准的80C51指令集和引脚相兼容。芯片闪存允许程序存储器在系统内重新编程，或者由常规的非易失性存储器编程器进行编程。通过将多功能8位CPU与系统内可编程flash结合在一个芯片上，Atmel的AT89S51是一款功能强大的微控制器，它为许多嵌入式控制应用提供了一种高灵活性和高性价比的解决方案。 AT89S51提供以下标准功能： 4K字节的闪存，128字节的RAM，32个I / O线，看门狗定时器，两个数据指针，两个16位定时器/计数器，一个5向量两级中断结构，一个全双工串行口，片上振荡器和时钟电路。此外，AT89S51设计了可降至零频率的静态逻辑操作和支持两种软件可选的节电工作模式。 在空闲模式下停止CPU的工作，但允许RAM 、定时器/计数器、串行接口和中断系统继续运行。掉电模式保存RAM中的内容，停止振荡器工作并禁止其它所有部件工作，直到下一个外部中断或硬件复位。 2 端口 P0端口是一个8位漏极开路双向I / O口。作为一个输出端口，每个引脚可接收8个TTL输入。对端口写“1”可作为高阻抗输入端用。在访问外部程序和数据存储器时，P0端口也可以被配置为多路低阶地址/数据总线。在访问期间P0具有内部上拉电阻。在Flash编程时，PO端口接收指令字节，而在程序校验时，输出指令字节，同时要求外接上拉电阻。 P1端口是一个带内部上拉电阻的8位双向I /O端口。P1端口的输出缓冲级可以接收四个TTL输入。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作为输入口。作为输入口时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL），Flash编程和程序校验期间，P1接收低8位地址。
P2端口是一个具有内部上拉功能的8位双向I/O端口。P2端口的输出缓冲器可以接收4个TTL输入。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，可以用作输入。当作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。在访问外部程序存储器或16位地址的外部数据存储器（例如执行 MOVX @ DPTR指令 ）时，P2端口送出高8位地址数据。 在访问8位地址的外部数据存储器（例如执行MOVX@RI指令）时，P2端口上的内容（即特殊功能寄存器（SFR)区中P2寄存器的内容），在整个访问期间不变。Flash编程或校验时，P2也可接收高位地址和其它控制信号。 P3端口是一个带有内部上拉功能的8位双向I/O端口。P3端口输出缓冲器可以接收4个TTL输入。对P3端口写入“1”时，他们被内部上拉电阻拉高并作为输入端口。当作输入端时，被外部拉低的P2端口将用上拉电阻输出电流（IIL）．P３端口还接收一些用于Flash编程和程序校验的控制信号。P3端口可以采用AT89S51的各种特殊功能，如下表所示。
3 特殊功能寄存器 特殊功能寄存器（SFR）的片内存储区分布如表3-1所示。 表3-1 AT89S51特殊功能寄存器分布图及复位值
值得注意的是，并不是所有的地址都被占用了，没有占用的地址也可能不能使用，读取这些地址通常会返回一个随意的数据。而写这些地址单元将产生不确定的影响。 不要用软件访问这些未定义的单元，这些单元是留作以后产品扩展用途的，复位后这些新的位将为0。 中断寄存器：各个中断控制位于IE寄存器，5个中断源的中断优先级控制位于IP寄存器。 表3-2 AUXR辅助寄存器 lt;剩余内容已隐藏，支付完成后下载完整资料 资料编号：[467284]，资料为PDF文档或Word文档，PDF文档可免费转换为Word
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