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IFAC-PapersOnLine 48-4 (2015) 354–361
On PLCs Control Program Hardware Implementation Selected Problems of Mapping and Scheduling
Adam Milik*
*Institute of Electronics, Silesian University of Technology of Gliwice, Poland (e-mail: adam.milik@ polsl.pl).
Abstract: The paper shows the FPGA dedicated method of mapping a PLC program written according to the IEC61131-3 standard. There is described complete synthesis process from the program description to hardware implementation through mapping and scheduling procedures. PLCs’ programming languages are translated into common intermediate graph form. It enables massive parallel implementation. There is presented an originally developed graph structure with attribute edges. Finally the graph mapping methodologies are discussed. A general hardware mapping concept and algorithms for utilizing specific FPGA components are presented. An efficient mapping of the DSP48 block is shown. It attempts to utilize all features of the block in pipelined calculation model. The consideration are summarized with implementation result comparison for general hardware mapping and with use of DSP48 units.
© 2015, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.
Keywords: PLC, FPGA, DSP48, LD, IL, SFC, DFG, high level synthesis, logic synthesis, reconfigurable hardware
- INTRODUCTION
Programmable logic controllers (PLCs) are present from early 70’s of XX century. They successfully replaced the mechanical and electro mechanical control systems offering better performance and reliability. Today PLCs become a standard in automation. The performance improvement of logic controllers is a main concern for automation system designers. Is it possible to improve the performance of a PLC? An attempt to answer this question is made by different researchers like in (Chmiel and Hrynkiewicz, 2010). One of the ideas that can significantly increase performance is fully custom hardware implementation of controller structure (Du et al. 2010, Economakos and Economakos 2012, Ichikawa et al. 2011, Mocha and Kania 2012, Milik 2013) It was even shown that controllers with advanced fuzzy algorithms are efficiently implemented in hardware (Wyrwoł and Hrynkiewicz, 2013). They are opposite to microprocessor based implementation that are based on serial processing of instructions. The serial processing concept is a source of significant performance limitation. It can be overcome by dedicated implementation of a hardware structure for a particular control task execution. In opposite to serial processing a massively parallel processing is possible with use of SRAM configured FPGAs. The application specific logic controller (ASLC) assures reprogramability through the static reconfiguration. It is worth to mention an interesting proposal of a dedicated PLC FPGA described in (Welch and Carletta, 2000).
The great success of PLCs is connected with easiness of programming. The method of program design has been standardized by the IEC61131-3 document and its subsequent revisions (Cenelec, 2013, John and Tiegelkamp, 2010). There
is described a wide range of programming languages from the simple textual instruction list (IL) to the high level structured text (ST). The ladder diagram (LD) graphical language is still very popular among automation designers. It has been inherited from design methodology based on electrical schematics of relay control systems. The SFC language is derived from GRAFCET (David, 1995). It offers ability of describing concurrent processes. All languages allow to express a control algorithm independently from a target hardware platform. Automation designers do not have to go into implementation details and concentrate on solving the control problem.
The ASLC (application specific logic controller) is implemented from a standard program with use of the high level synthesis covering: translation, scheduling and mapping. Each of those steps requires knowledge and skills from areas like: compilation, digital synthesis, operation schedule, hardware mapping. To make the application specific logic controller competitive to standard PLCs the set of EDA tools must be created. This paper is a continuation of research program over the ASLC implementation (Milik and Hrynkiewicz 2012 and 2014, Milik 2013). It briefly recalls basic definitions and recently presented methods of intermediate program representation. Than it moves to stages devoted to technology mapping. There are discussed an early mapping stages, scheduling problems and different mapping strategies targeted to specific components of contemporary FPGAs represented by the Xilinx Spartan 6 family.
- THE PLC PROGRAM INTERMEDIATE
REPRESENTATION
The control program must be translated into a form that is suitable for further handling accommodated to hardware
2405-8963 © 2015, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved. Peer review under responsibility of International Federation of Automatic Control.
10.1016/j.ifacol.2015.07.060
synthesis. It is expected that intermediate representation allows not only revealing the program semantics but also operation dependencies. It is important to reveal all
independent operations for possible parallel execution in hardware. An enhanced data flow graph (EDFG) has been
Q is the set of variables associated with outputs and internal nodes. The above sequential processing is transformed to parallel processing by introducing an auxiliary variables set D as follows:
proposed. The flow graphs are
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