Phase-change memory (PCM) has several benefits including low cost, non-volatility, byte-addressability, etc., and limitations such as write endurance. There have been several hardware approaches to exploit the benefits while minimizing the negative impact of limitations. Software approaches could give further improvements, when used together with hardware approaches, by taking advantage of write behavior present in the program, e.g., write behavior on dynamically allocated data, which is hardly captured by hardware approaches. This work proposes a software design methodology to reduce costly PCM writes. First, on top of existing hardware approach such as Flip-N-Write, we advocate exploiting the capability of PCM bit-level differential write in the software by judiciously reusing previously allocated memory resource. In order to avoid wear-out incurred by the reuse, we present software-based wear-leveling methods that distribute writes across PCM cells. In order to further reduce PCM writes, we propose identifying data, the loss of which does not affect the functionality of the underlying software, and then diverting write traffic for those data items to volatile memory. To evaluate the effectiveness of these methods, as a case study, we applied the proposed methods to the design of journaling in SQLite, which is an important database application commonly used in smartphones. For the experiments, we used an in-house PCM-based prototype board. Our experiments with four representative mobile applications show that the proposed design methods, which is applied on top of the hardware approach, Flip-N-Write, result in 75.2% further reduction in total bit updates in PCM, on average, without aggravating wear-out compared with the baseline of PCM-based journaling, which is based only on the hardware approach. Also, the proposed design methods result in 49.4% reduction in energy consumption and 52.3% reduction in runtime compared to a typical FIFO management of free resources.
Phase-change memory (PCM) provides important benefits such as scalability (better than dynamic random access memory, DRAM), non-volatility, short latency, and byte-addressability (unlike the page-level access granularity of Flash memory). Among several possibilities of PCM application, e.g., storage, main memory, and cache, its application to main memory is considered to be the most promising one due to the lower area cost (more than 2X lower cost than DRAM) and standby power (due to non-volatility). Lee et al. [2009] presented a PCM-only main memory architecture to replace conventional main memory based on DRAM. Qureshi et al. [2009a] proposed a hybrid DRAM and PCM main memory structure and showed the benefit of PCM usage on the main memory, i.e., higher program performance due to reduced disk accesses and lower system energy consumption due to reduced runtime and low standby power than in the system with conventional DRAM-only main memory under a similar memory cost. Zhou et al. [2009] presented a tiered DRAM and PCM main memory to reduce PCM writes.
PCM subsystems on main memory buses are promising due to their broad applica-bility, covering both main memory (e.g., for use as background main memory [Qureshi et al. 2009a] or tiered main memory [Zhou et al. 2009]) and a portion of storage (e.g., for use with journaling or memory page swapping [Fang et al. 2011]). However, in such systems, write-related problems (especially write endurance) become critical issues since such systems are expected to experience more frequent writes than in PCM storage-only applications [Akel et al. 2011; Kim et al. 2014].
There are several hardware-based approaches that address write endurance to reduce bit updates by differential write [Yang et al. 2007] and data coding (including Flip-N-Write [Cho and Lee 2009]) and maximum bit updates (which usually determine PCM lifetime) by evenly distributing writes across PCM cells in wear leveling [Qureshi et al. 2009b; Seong et al. 2010; Yoon et al. 2012; Liu et al. 2013; Zhao et al. 2014]. Such hardware approaches are effective in mitigating the write endurance problem. However, they have a significant limitation in that the program behavior is not fully exploited to address the write endurance problem. It is critical to make the best use of the data write behavior in the software program running on the PCM. For instance, in the case of wear leveling, when writes are concentrated on a small amount of hot data, hardware approaches have a clear limitation in evenly distributing writes since they do not utilize exact write behavior, which could be gathered by the software program. Instead, hardware approaches mostly rely on past history, e.g., write counts, in order to predict future write behavior [Yoon et al. 2012]; such a prediction often fails to fully capture the write behavior of program. This problem becomes critical especially when frequent dynamic memory allocations and de-allocations are performed in the software program where the physical address-based information of past write history, which hardware approaches rely on, is likely to be useless.
In order to exploit bit-level differential write for total bit update reductions in real PCM chips, we propose a software design methodology that reuses previously allocated PCM resources in the case of frequent and small-sized overwrites. This in turn reduces data differences at the bit level and thereby reduces PCM writes. Since too much reuse might worsen wear-out problems, we design wear-leveling-conscious data structures that utilize XOR flags and overprovision spare resources to address the localized wear-out incurred by reuse. In addition, we reduce the total amount of PCM traffic by identifying quasi-non-volatile and non-functional data from existing non-volatile data and allocating such data in volatile memory.
We performed a case study of software design for PCM using SQLite journaling on our PCM-based prototy
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相变存储器(PCM)有几个优点，包括低成本、非挥发性、字节寻址性等，以及写持久性等限制。有几种硬件方法可以利用这些优点，同时最小化限制的负面影响。当与硬件方法一起使用时，软件方法可以通过利用程序中出现的写行为(例如，对动态分配的数据的写行为，这很难被硬件方法捕获)提供进一步的改进。这项工作提出了一种软件设计方法，以减少昂贵的PCM写。首先，在现有的硬件方法(如Flip-N-Write)的基础上，我们提倡通过明智地重用以前分配的内存资源，在软件中利用PCM位级差分写的能力。为了避免重用带来的磨损，我们提出了基于软件的磨损均衡方法，该方法在PCM单元之间分发写操作。为了进一步减少PCM写操作，我们建议识别数据(丢失数据并不影响底层软件的功能)，然后将这些数据项的写流量转移到易失性内存中。为了评估这些方法的有效性，我们将这些方法作为一个案例研究，应用于SQLite中日志记录的设计，SQLite是智能手机中常用的一个重要数据库应用。在实验中，我们使用了一个内部基于pcm的原型板。我们的实验与四个代表移动应用表明,该设计方法,硬件方法的应用上,Flip-N-Write,导致总更新在PCM进一步减少75.2%,平均而言,没有加重磨损与基线相比PCM-based日志记录,这是只基于硬件的方法。此外，与典型的免费FIFO管理相比，所提出的设计方法可以减少49.4%的能耗和52.3%的运行时间资源。
相变内存(PCM)提供了一些重要的好处，比如可伸缩性(比动态随机访问内存、DRAM更好)、非挥发性、短延迟和字节寻址能力(不像闪存的页面级访问粒度)。在PCM应用的几种可能性中，如存储、主存、高速缓存等，其在主存上的应用被认为是最有前途的一种，因为它具有较低的面积成本(比DRAM低2倍以上)和备用电源(由于非挥发性)。Lee等[2009]提出了一种基于DRAM的pcm专用主存架构来替代传统的主存。Qureshi等[2009a]提出了一种DRAM与PCM混合的主存结构，并展示了使用PCM对主存的好处，即在相同的内存成本下，与传统的只使用戏剧主存的系统相比，由于减少了磁盘访问而具有更高的程序性能，由于运行时减少和低备用电源而具有更低的系统能耗。Zhou等[2009]提出了一种分层DRAM和PCM主存来减少PCM写入。
PCM子系统在主内存总线承诺由于其广泛的applica-bility,包括两个主要的记忆(例如,用作背景主存(库雷希et al . 2009年)或分层主内存[周et al . 2009])和部分存储(例如,使用日志记录或内存页面交换[方et al . 2011])。然而，在这样的系统中，与写相关的问题(尤其是写持久性)成为关键问题，因为这样的系统预期会比只存储PCM应用程序经历更频繁的写操作[Akel et al. 2011;Kim等，2014]。
有几种基于硬件的方法,地址写耐力降低一点更新微分写(杨et al . 2007]和数据编码(包括Flip-N-Write[曹和李2009])和最大点更新(通常确定PCM一生)均匀地分布在PCM细胞穿平整写道[库雷希et al . 2009 b;Seong et al. 2010;Yoon等，2012;Liu等，2013;赵等。2014]。这种硬件方法可以有效地缓解写持久性问题。然而，它们有一个显著的限制，即没有充分利用程序行为来解决写持久性问题。充分利用运行在PCM上的软件程序中的数据写行为是至关重要的。例如，在磨损均衡的情况下，当写集中于少量热数据时，硬件方法在均匀分布写方面有明显的限制，因为它们没有利用可以由软件程序收集的确切的写行为。相反，硬件方法主要依赖于过去的历史，例如写计数，以预测未来的写行为[Yoon et al. 2012];这样的预测常常不能完全捕获程序的写行为。这个问题变得非常关键，特别是在软件程序中执行频繁的动态内存分配和反分配时，硬件方法所依赖的基于物理地址的过去写历史信息很可能是无用的。
为了在实际的PCM芯片中利用位级差异写来减少总的位更新，我们提出了一种软件设计方法，在频繁和小规模重写的情况下重用以前分配的PCM资源。这进而减少了位级别上的数据差异，从而减少了PCM写入。由于过多的重用可能会加剧磨损问题，所以我们设计了具有磨损级别意识的数据结构，这些数据结构利用XOR标志，并提供过多的备用资源来解决重用导致的局部磨损。此外，我们通过从现有的非易失性数据中识别准非易失性和非功能性数据，并在易失性内存中分配这些数据，减少了PCM流量的总量。
我们在基于PCM的原型板上使用SQLite日志进行了PCM软件设计的案例研究。通过对四个具有代表性的移动应用程序的实验表明，与典型的FIFO自由资源管理相比，我们提出的方法在处理时间上减少了52.3%，在能源消耗上减少了49.4%。与PCM上对空闲资源的典型FIFO管理相比，在现有硬件方法Flip-N-Write的基础上，我们的重用方法在不增加最大位更新的情况下平均减少了75.2%的总位更新。在我们未来的工作中，我们的目标是用一般的软件设计框架，例如分析器和编译器，来展示区分写意识软件设计的好处。
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